1. Field of Invention
The invention relates to bond pad structures for integrated circuits (IC) or semiconductor devices that use Al as the last metal for bond purposes, and employs tungsten or a tungsten compound layer as the top layer of the last metal stack, and wherein the tungsten or tungsten compound layer may function as a redundancy or anti-reflecting coat on top of the top metallization layer in the bond pad structure.
2. Description of the Prior Art
A passivation layer etching process for memory arrays with fusable links is disclosed in U.S. Pat. No. 6,180,503 B1. The memory arrays with fusable links are obtained by etching the laser access opening in two steps using a transient etch stop layer between the first and second step. After a fuse is formed in a polysilicon level, an etch stop pad is patterned in a higher level metal or polysilicon level over the rupture zone of the fuse. The fuse access opening is then partially formed concurrent with a via etch which penetrates a thick IMD layer. The etch stop pad limits the penetration over the rupture zone to only the IMD layer. The etch stop pad is removed during a metal patterning etch. The second and final portion of the access opening is then formed during patterning of the passivation layer. Because the etch stop pad has already been removed at passivation etching, the bonding pads opening and the final fuse access opening can be accomplished by a single mask.
U.S. Pat. No. 6,319,758 disclose redundancy structures in self-aligned contact processes. The redundancy structure for implementation of redundant circuits within a IC placed on a semiconductor substrate includes a fusable link.
The fusible link is formed of a layer of a conductive material deposited upon an insulating layer of the semiconductor substrate connected between the redundant circuits and other circuits present on the integrated circuit. The insulating layer is generally a layer of field oxide placed on the surface of the semiconductor substrate. The layer of conductive material is either formed of a metal such as Aluminum (Al) or Tungsten (W), a heavily doped polycrystalline silicon, or an alloy of a metal such as Tungsten (W) and a heavily doped polycrystalline silicon.
A bond pad structure and method of fabricating the same is disclosed in U.S. Pat. No. 6,365,970 B1. The bond pad structure comprises:                a lower metal layer formed over the predetermined area;        a dielectric layer formed on the lower metal layer, the dielectric layer having via openings formed through the dielectric layer on the first, second and third areas only, respectively;        a first diffusion barrier layer formed over the dielectric layer and the sidewalls and bottom of the via openings;        via plugs formed by filling a metal material into the via openings;        a second diffusion barrier layer formed over the first diffusion barrier layer and via plugs; and        an upper metal layer formed over the second diffusion barrier layer.        
U.S. Pat. No. 5,882,999 discloses a process for metallization of an insulator layer in integrated circuits. The process involves depositing an antireflective coating layer of a material such as TiN over the insulator layer, patterning both the ARC and the insulator with a series of channels or apertures vias and depositing a metal such as tungsten over the ARC and in the channels and apertures.
A non-reactive anti-reflection coating is disclosed in U.S. Pat. No. 5,834,125. The anti-reflective coating is comprised of a barrier layer and an anti-reflective layer. The barrier layer is comprised of a material which prevents reactions between the anti-reflective layer and underlying layers or substrates, does not make the anti-reflective layer reflective, and preferably does not react with either the reflective layer or the anti-reflective layer. In particular embodiments of the invention, the barrier layer is a thin layer of silicon dioxide SiO2 or silicon nitride Si3N4, and the anti-reflective layer is titanium-tungsten TiW, titanium nitride TiN, or amorphous silicon.
Tao et al., CHARACTERIZATION AND MODELING OF ELECTROMIGRATION FAILURES IN MULTILAYERED INTERCONNECTS AND BARRIER LAYER MATERIALS, IEEE Transactions On Electron Devices, Volume 43, No. 11, November 1996, pages 1819-1824, disclose electromigration performance of TiN/Al-alloy/TiN multilayered interconnects and TiN and TiW barrier layer materials, wherein damaged healing observed in multilayered interconnects is demonstrated to the due to the stress induced during Al electromigration instead of joule heating.
There is a need to find and deploy a substitute for Ti and Ti compounds in lieu of the fact that Ti and its compounds are difficult and slow to remove by fluorine chemistry, when the Ti materials are used as top layers on the last metal stack of an IC or semiconductor device, such as a bond pad structure, where bond pad structures provide an IC chip with location for bonding wires or other connectors. The need is apparent when it is considered that, when the IC chip is fabricated, yield of the chip is directly related to the reliability of the bond pad on itself. This is so because, when the bond pad is manufactured, the bond pad of the IC chip tends to deteriorate from damages during later probe test procedures and wire bonding processing.